Our Personal Digital Assistants, SatNavs and other electronic devices boast more and more interactive features. They have become fundamental data, communication and navigation tools in our daily lives. As the electronic circuits found within these devices are becoming more and more complex, designing them represents a real challenge. The TARAN team focuses on innovative circuit architecture and design in order to advise system developers...
The TARAN team works on reprogrammable chip systems: software architecture, algorithms and compilation.
Areas of research
Promotes programmable software architecture research through three approaches: studying the conception of new reprogrammable platforms; studying software compilation/related storage and exploring the interaction between algorithms and material hardware architecture.
- Conception of reprogrammable software architecture and bespoke designed in-chip systems for specific applications focusing on energy efficiency, ease of use and reconfiguration management
- Reprogrammable software architecture languages
- Flexible reprogramming management, compatibility with the operating system
- Reprogrammable memory structure
- Flexible arithmetic operators
- Multi-mode accelerators
- Conception of compilation, storage and coding transformation techniques applicable to these software architectures
- Pattern-recognition compilation programming
- Storage accelerators for C-loop programs. Automatic transformation from floating-point units to fixed-point units
- Multi-mode storage accelerators
- Power-restricted optimisation, algorithm resourcing and signal processing, algorithm interaction architecture
- Analytical assessment of fixed-point unit systems
- Pre-programming of 4G/MIMO systems
- MIMO systems adapted to sensor networks
- Generating correctly randomised number sequences at high speeds